The present disclosure relates generally to processor cores, and more specifically, to simultaneous multithreading (SMT) on the processor cores.
Simultaneous multithreading allows various core resources of a processor to be shared by a plurality of instruction streams known as threads. Core resources can include instruction-execution units, caches, translation-lookaside buffers (TLBs), and the like, which may be collectively referred to generally as a core. A single thread, whose instructions access data, typically cannot utilize the full core resource due to the latency to resolve data located in the memory nest. Multiple threads accessing data sharing a core resource typically result in a higher core utilization and core instruction throughput, but individual threads may experience slower execution. In a super-scalar processor simultaneous multithreading (SMT) implementation, multiple threads may be simultaneously serviced by the core resources of one or more cores.